module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    parameter find=0,A=1,B=2,C=3,success=4,count_state=5,done_state=6;
    reg [2:0] state;
    reg [2:0] next_state;
    reg [1:0] count;
    always @(posedge clk) begin
        if(state==success)
            count<=count+2'd1;
        else if(count==2'd3)
            count<=2'd0;
        else
            count<=2'd0;
    end
    
    always @(*) begin
        case(state)
            find:
                begin
                    if(data)
                        next_state=A;
                    else
                        next_state=find;
                end
            A:
                begin
                    if(data)
                        next_state=B;
                    else
                        next_state=find;
                end
            B:
                begin
                    if(data)
                        next_state=B;
                    else
                        next_state=C;
                end
            C:
                begin
                    if(data)
                        next_state=success;
                    else
                        next_state=find;
                end
            success:
                begin
                    if(count==2'd3)
                        next_state=count_state;
                    else
                        next_state=success;
                end
            count_state:
                begin
                    if(done_counting)
                        next_state=done_state;
                    else
                        next_state=count_state;
                end
            done_state:
                begin
                    if(ack)
                        next_state=find;
                    else
                        next_state=done_state;
                end          
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)
            state<=find;
        else
            state<=next_state;
    end
    assign shift_ena=(state==success);
    assign counting=(state==count_state);
    assign done=(state==done_state);
endmodule